1. Field of the Invention
The present invention relates to signal detection, in particular to signal detection for binary signal based on a low resolution analog-to-digital conversion and a logical operation on an output of the conversion.
2. Description of Related Art
Binary signaling is a popular scheme widely used in serial data link; for instance, SATA (Serial Advanced Technology Attachment). In such a serial data link, a bit stream is transmitted at a certain nominal rate fs in accordance with a first clock signal; each bit is either a logical “1” or a logical “0”; a logical “1” is represented by a voltage of a first level of a certain nominal duration Ts, where Ts=1/f, while a logical “0” is represented by a voltage of a second level of the certain duration Ts; and as a result, the bit stream is represented by a voltage signal toggling back and forth between the first level and the second level in accordance with a pattern of the bit stream. The voltage signal is received by a receiver, which needs to produce a second clock signal (often referred to as the recovered clock signal) that tracks the first clock signal and detecting the bit stream by sampling the voltage signal in accordance with the recovered clock signal.
FIG. 1A shows an exemplary received signal waveform, as observed on an oscilloscope, of a binary signaling system. Such a waveform is referred to as an “eye diagram.” In a prior art receiver, a binary phase detector, also known as binary phase detector, is used for adjusting a timing of the recovered clock. The principle of binary phase detector is well known in prior art and thus not described in details here. In a clock-data recovery (CDR) circuit based on using a binary phase detector, the timing of the recovered clock is adjusted in a closed loop manner so as to align a falling edge of the recovered clock with a bit transition (102, 104). If the eye diagram is symmetrical, as in the case of FIG. 1A, then the rising edge of the recovered clock will be aligned with the timing of “maximum eye opening” (101, 103, 105) as long as the falling edge of the recovered clock is aligned with the timing of the bit transition (102, 104), provided the recovered clock has 50% duty cycle. If the eye diagram is not symmetrical, as in the case of FIG. 1B, the timing of the falling edge of the recovered clock will still be aligned with the bit transition (112, 114), but the timing of the rising edge (111, 113, 115) is no longer aligned with the timing of the maximum eye opening (116, 117, 118), provided the recovered clock has 50% duty cycle. In this case, the clock-data recovery circuit fails to sample the received signal at the optimum sampling instant (which is the timing of the maximum eye opening).
This present invention seeks to further improve the performance in data recovery by mitigating a detrimental effect of ISI (inter-symbol interference) due to channel dispersion. An exemplary eye diagram of a received signal suffering from ISI due to channel dispersion is shown in FIG. 1C. Although the eye is still open, i.e. the two levels for the binary signaling are still distinguishable at an optimum sampling instant (121, 123), the eye opening is small and the receiver is prone to making an erroneous decision in presence of circuit noise or coupled noise. What is needed is a method to make the signal detection more reliable.